Analog Design Engineer

• Help design the building blocks of a PLL.
• Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.
• Work closely with layout engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution.

• 3-5 years of professional experience in the semiconductor industry.
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm/5nm.
• Hands-on design experience in performance analog and hybrid Phase Locked Loops, analog-to-digital (Client), digital-to-analog (DAC) data converter, VCO, LDO, bandgap, charge pump, op-amps, interpolator circuits.
• Experience with the following is a plus: Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.
• Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis.
• Helic/EMX is a plus.
• Have good experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.
• Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like).
• Proficiency in scripting languages like Perl, Python, matlab etc. is a plus.
• Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy,
• Possess strong analytical/problem solving skills and pronounced attention to details,
• Must be a self-starter, and able to independently drive tasks to completion,
• Master’s in electrical engineering or equivalent preferred.

Last updated on Oct 10, 2023