Job Description...Understand the architecture of the Display IP and functional block being designed
Build SystemVerilog and/or C/C++ models and test sequence libraires for simulation
Build test bench and monitors for DUT
Compose test and coverage plan, and validation vectors to ensure functional completeness
Debug function/performance bugs of Display IP in Emulation and Simulation Environments
Experience Required:
3+ year(s) of proven verification experience on large ASIC development projects or equivalent embedded programming experience with a deep understanding of hardware architecture
Very strong background in C/C++/OOO coding techniques
Experience with Verilog and/or System Verilog
Experience working with Cadence NCSIM, Synopsys VCS or equivalent
Experience working with UVM, OVM or equivalent
Experience with scripting languages, Ruby/Python/Tcl/BASH/etc.
Working knowledge of UNIX/Linux operating systems and debug tools
Interest in developing custom verification tools and driving new test methodologies
Strong analytical skills and attention to detail
Excellent written and communication skills
Team player with proven leadership skills •
Last updated on Dec 15, 2020