ASICS Engineering - Engineer, Senior

Job Title: ASICS Engineering - Engineer, Senior|(5019088-1)

Duration: 24 months

Location: Markham, ON

Hybrid with at least 3 days in office

TOP 5 REQUIRED SKILLS:
1. 3+ Years Professional or academic ASIC hardware design and/or implementation experience. (New graduates should have ASIC design internship or co-op experience.)
2. Proficiency with Verilog/VHDL RTL design languages and ability to write clean, readable, synthesizable RTL.
3. Experience in logic synthesis and STA using Client and/or Cadence tools.
4. Working Experience in Implementing ECOs
5. Experience in Power intent validation (CLP)

TECHNOLOGIES:
Scripting Languages
Client
Cadence
CDC Lint

REQUIRED EDUCATION:
Bachelors or Masters Degree in Computer Science, Electrical Engineering, Computer Engineering or related field

PHYSICAL REQUIREMENTS:
N/A

DRIVING REQUIREMENTS:
N/A

KEY WORDS:
ASIC
Hardware Design
Cadence
Client
Lint
CDC

JOB DESCRIPTION:
As part of our team your responsibilities will be focused on key ASIC implementation tasks such as:
Synthesis
Timing Constraints
Implementing ECOs
STA
Power intent validation (CLP)
Lint
Power Analysis Tasks
CDC validation
Model and analyze performance, area, power, and system cost tradeoffs for different micro-architectures
Contribute to implementation methodologies/ flows
Specific responsibilities will be a function of project and team needs and may vary over time. In addition to implementation tasks the successful candidate may also be asked to perform ASIC design tasks including some RTL development.