Duration:0-12 month(s)
Description/Comment:CM&T
Level 9
Remote: Hybrid
Local: Preferred
Education: Bachelor's
VISA: GC & USC preferred
MUST HAVE: 1.UVM 2. Wreal 3. Real Number Modeling
Semiconductor Design and Development - Design Integrated Circuits (IC) that power everyday electronic devices. Design custom or semi-custom silicon used on electronic devices, cloud infrastructure, machine learning, and AI computational platforms. Work across the entire silicon design lifecycle, including system architecture, design verification, RTL digital design, physical design, design for test (DFT), and Emulation.
5+ years hands on experience with
System modeling languages: MATLAB, RTL, System Verilog, Verilog-AMS with wreal
SystemVerilog testbench development from scratch
In depth understand of System Verilog including RNM (Real Number Modeling) coding for analog blocks
Ability to develop and modify UVM based env for mixed signal including Verilog-AMS and wreal
Solid understanding of analog circuit fundamentals
Ability to read analog schematics and extract related main functionality
Verification of mixed signal designs and sub-systems using advanced verification methodologies
Experience in writing scripts in languages such as perl, python.
Proficiency in running mixed-signal simulations and debugging across digital/analog boundary
Strong communications skills written & verbal
Experience creating executable verification plan
Experience creating cover groups and assertion based checkers for MS designs
Responsibilities
Interact with analog designers, read schematics and understand basic analog functions.
Understand digital models of analog and compare with analog functions
Work with digital (real number models) of main analog components and devise methods to check for functional equivalence of these digital models against analog functions
Develop verification-plan for block and chip-level verification working closely with design, architecture and DV teams
Architect the testbench and develop verification environment using UVM-MS
Create and maintain UVM based MS verification environments at both block and chip-level
Integrate the block testbench in chip-level UVM environment and verify integration
Create checkers for mixed-signal designs, create and debug assertions
Create functional coverage for mixed-signal designs
Stimulus generation using constrained random and directed tests
Debug complex chip digital-on-top testbenches and seek root causes of failures
Debug complex chip analog-on-top testbenches and seek root causes of failures
Coverage closure for both analog & digital - close the loop with executable spec to gauge functional completeness.
Project manage and track DV activities
Scripting and automation with python, perl
Additional Job Details:1 - Electrical Engineering (P3 - Advanced) | 2 - Electronic Design Automation (EDA) (P3 - Advanced) •
Last updated on Jun 7, 2023