Senior Engineer FPGA/Design

What You’ll Do

The Memory Solutions Lab (MSL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash, SRAM memory. MSL’s vision is to solve key problems and optimize architecture solutions for Cloud & Data center environments. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

We are currently looking for a Senior FPGA Engineer to join our team in San Jose, CA. The Candidate will be a key technical member of MSL, Datacenter Device Solutions (DCDS) Group.  He or she will join a team of experts in researching and developing innovative data center/ cloud networking, storage, and compute ASIC/ FPGA and system solutions. The ideal candidate must have prior experience developing leading edge solutions on FPGAs in at least one of the areas: memory hierarchy, storage, networking, or embedded computing.

 Location: Hybrid, working onsite at our San Jose, CA headquarters 3 days a week, with the flexibility to work remotely the remainder of your time.

Job ID: 42253

• FPGA architecture, microarchitecture, RTL design, and verification
• Lab bring-up, lab test and validation of an FPGA prototypes
• Develop new RTL IP for high performance PoCs
• Research next generation memory and storage controller features in an FPGA environment
• Research, evaluate and integrate acquired third party Intellectual Property (IP)
• Research emerging technology standards and map to optimal implementation in FPGA
• Work with hardware/ software architects developing one-of-a-kind innovative FPGA prototypes and contribute to feasibility studies & developing solutions
• Assist software architects developing Linux/ Windows device driver, test and debug.

What You Bring 

• Bachelor's with 5+ years of relevant industry experience, or Master's with 3+ years or PhD in engineering or related technical field preferred
• Four years of industry experience in FPGA/ASIC/SoC RTL development
• Demonstrated ability with FPGA design tool flows, synthesis, timing analysis, partitioning, FPGA programming, bring up and testing
• In-depth background in HDL development, Verilog coding, integration, synthesis, debug, simulation, test bench creation and debug using CAD tools (Synopsys, Mentor, Cadence, or FPGA tools)
• Hands-on experience with hardware board bring-up, server system integration and software integration with FPGAs
• Experience and exposure to PCIe, CXL, NVMe, AXI, DDR3/4/5 protocols
• Must be highly motivated with excellent verbal and written communication skills.
• Demonstrated attention to detail
• Ability to meet aggressive project deadlines in a team environment
• Ability to work successfully with cross-functional teams, including coordinating across organizational boundaries and geographies.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

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Last updated on Aug 20, 2024